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NXP Semiconductors
PCA9533
4-bit I 2 C-bus LED dimmer
SDA
t BUF
t r
t f
t HD;STA
t SP
t LOW
SCL
t HD;STA
t SU;STA
t SU;STO
P
S
t HD;DAT
t HIGH
t SU;DAT
Sr
P
002aaa986
Fig 19. De?nition of timing
protocol
START
condition
(S)
t SU;STA
bit 7
MSB
(A7)
t LOW
t H IG H
bit 6
(A6)
1 /f
SCL
bit 0
(R/W)
acknowledge
(A)
STOP
condition
(P)
SCL
SDA
t BUF
t r
t f
t HD;STA
t SU;DAT
t HD;DAT
t VD;DAT
t VD;ACK
t SU;STO
002aab175
Rise and fall times refer to V IL and V IH .
Fig 20. I 2 C-bus timing diagram
12. Test information
V DD
open
PULSE
GENERATOR
V I
V DD
DUT
V O
RL
500 ?
V SS
RT
CL
50 pF
002aab880
R L = load resistor for LEDn. R L for SDA and SCL > 1 k ? (3 mA or less current).
C L = load capacitance includes jig and probe capacitance.
R T = termination resistance should be equal to the output impedance Z o of the pulse generators.
Fig 21. Test circuitry for switching times
PCA9533_3
? NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 27 April 2009
16 of 24
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